Freescale Semiconductor /MKL28T7_CORE1 /TRNG /MCTL

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Interpret as MCTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (00)SAMP_MODE 0 (00)OSC_DIV 0 (UNUSED)UNUSED 0 (TRNG_ACC)TRNG_ACC 0 (RST_DEF)RST_DEF 0 (FOR_SCLK)FOR_SCLK 0 (FCT_FAIL)FCT_FAIL 0 (FCT_VAL)FCT_VAL 0 (ENT_VAL)ENT_VAL 0 (TST_OUT)TST_OUT 0 (ERR)ERR 0 (TSTOP_OK)TSTOP_OK 0 (PRGM)PRGM

OSC_DIV=00, SAMP_MODE=00

Description

TRNG Miscellaneous Control Register

Fields

SAMP_MODE

Sample Mode

0 (00): use Von Neumann data into both Entropy shifter and Statistical Checker

1 (01): use raw data into both Entropy shifter and Statistical Checker

2 (10): use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker

3 (11): undefined/reserved.

OSC_DIV

Oscillator Divide

0 (00): use ring oscillator with no divide

1 (01): use ring oscillator divided-by-2

2 (10): use ring oscillator divided-by-4

3 (11): use ring oscillator divided-by-8

UNUSED

This bit is unused but write-able. Must be left as zero.

TRNG_ACC

TRNG Access Mode

RST_DEF

Reset Defaults

FOR_SCLK

Force System Clock

FCT_FAIL

Read only: Frequency Count Fail

FCT_VAL

Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT.

ENT_VAL

Read only: Entropy Valid

TST_OUT

Read only: Test point inside ring oscillator.

ERR

Read: Error status

TSTOP_OK

TRNG_OK_TO_STOP

PRGM

Programming Mode Select

Links

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